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Digital Logic Design (The Game)

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Welcome to Digital Logic Design (The Game)! This game combines elements of traditional incremental games like Cookie Clicker with more complex elements designed apeal to someone interested in clicking less and thinking more.

In this game you will take on the role of a digital logic designer. You will be presented with designs you must implement using logic gates. The design will be simulated to verify that your implementation fulfills the requirements. Then you will be able to sell your design to generate cash to purchase upgrades and additional designs.

However, there are 2 complications.

First, you only have one logical primitive available to you, the NAND gate. If you need something else, an OR gate for example, you will have to design it yourself using NAND gates. In fact, many of the first designs available to work on will be other simple logic gates.

Second, you can't create NAND gates from thin air. NAND gates are built from silicon (Si). In order to sell your designs you must have enough silicon to create all the NAND gates required for that design. The number of NAND gates required is defined by your own design implementation so try to minimize the number of NANDs you use. Silicon is collected via mining, a task you will be performing frequently at first but perhaps less often as you are able to purchase upgrades.

The user interface has been split into multiple tabs. Navagate between tabs by pressing the buttons at the top of the page. Navigate between documents by selecting the desired document at the top of this tab. To begin, select and follow the "Tutorial 1" document.

Questions, comments, suggestions, and discussion can be posted on reddit.com/r/dldtg

Your first task will be to complete the NAND design. This will be easy because the NAND blueprint is free and you already have the NAND gate available as a primitive.

You'll purchase the blueprint so it will be available for you to implement. Then you'll load up the NAND test fixture and run your first verification simulation. The test fixture is fully complete so you don't need to make any changes.

  1. Press the ↷ button to the right to pop this tutorial out of the page.
  2. Go to the Business tab and purchase the NAND blueprint.
  3. Go to the Design tab.
  4. Select the NAND design.
  5. Read the design description and follow its instructions.

After you've completed tutorial 1 proceed to tutorial 2.

Your second task will be to complete the NOT design. This time you will need money to purchase the blueprint and you'll need to design and implement the NOT gate.

To get money, you will need to sell NANDs but you can't do that without first mining some silicon. To implement the NOT gate you'll probably want to refer to the primitives document and the netlist format document.

  1. Go to the Business tab to check the price of the NOT blueprint, the sale price of the NAND design, and the cost of the NAND design in Si.
  2. Go to the Si Mine tab and mine enough Si so you can sell enough NANDs to buy the NOT blueprint.
  3. Go to the Business tab, sell some NANDs and buy the NOT blueprint.
  4. Go to the Design tab.
  5. Select the NOT design.
  6. Read the design description.
  7. Press the Load Test button.
  8. Using the available primitives and valid netlist format (see other documents for references), implement your NOT design above the test fixture loaded in the previous step. You're going to need to add text to the top of the netlist that looks something like this:
  9. Press the Init\Reset button.
  10. Press the Run button.
  11. Review the log messages and iterate over the previous 3 steps until you have successfully implemented a NOT gate

When you run your design, previously completed designs that appear above the current design in the available designs list will be automatically available. For example, you could use your successful NOT design in a future design without needing to retype the definition of NOT. To disable this feature, uncheck the "Automatically include prior designs" checkbox on the info tab.

It's also possible to load designs from a file if you prefer to edit with your own text editor. Create a new text file anywhere on your computer. Edit the file with your favorite text editor. You can use the Choose File and Prepend File buttons on the Design tab to load your designs directly from the file into the netlist textbox.

You've finished all the tutorials. Try to purchase and implement all the remaining designs. You'll find upgrades available on the Upgrades tab that will help you along the way.

Good Luck and remember that you can always visit reddit.com/r/dldtg for questions, comments, suggestions, and discussion.

A netlist defines logical blocks, their hierarchy, and their connections. A logical block can contain input and output ports, internal nets, and child blocks. A block must be defined before it can be used. First a quick and dirty example to get you started and a detailed annotated example follows it.

#Create a new block called "SimpleBlock". #It has input ports A and B and an output port Z. #Create an instance of a NAND named MyNAND. #The NAND has 2 input ports and one output port. #Connect the input ports A and B to the NAND's 2 input ports and #connect the output port Z to the NAND's output port. DEF SimpleBlock PORT IN A PORT IN B PORT OUT Z INST MyNAND NAND A B Z ENDDEF

This simple example can also be thought of in programming terms as something like the following:

Function SimpleBlock (input A, input B) {
  return NAND(A, B);

Just remember that you can have multiple output ports.

Now for the complete example.

#Everything on a line after a # character is ignored. #Blank lines are ignored. #case is ignored. Everything is converted to UPPERCASE internally. #begin the definition of a logical block with the DEF command DEF myBlock #DEF <block name> #multiple whitespace characters can occur before/after a command and between arguments #The PORT command defines the inputs and outputs a block uses to communicate with it's parent block. PORT IN MYINPUT PORT IN MYINPUT2 #PORT <IN|OUT> <port name> #The order the ports are defined is the same order they must appear when your block is instantiated. PORT OUT MYOUTPUT #The NET command defines internal nets that can be used to connect your block's child blocks' ports to each other. #Nets and ports share the same namespace so you can not create a port with the same name as a net and vice versa. NET NET1 #NET <net name> #The INST command creates an instance of a child block and connects nets or ports from your block # to the child block's IN and OUT ports. #INST <instance name> <block name> <port list> INST MYNAND NAND MYINPUT MYINPUT2 NET1 #PORT, NET, INST can occur in any order as long as the PORTs and NETs used by an INST are defined before they are used. PORT IN ANOTHERINPUT INST NAND2 NAND NET1 ANOTHERINPUT MYOUTPUT #Any nets/ports can be provded with vector notation. Vectored PORT/NET statements expand to multiple PORT/NET # statements in order of the vector from left to right. in this case the VECTOR<1> port would be before VECTOR<0>. # You can use vectors in any order <high:low> or <low:high> #When vectors are used to connect to instances they are expanded and work as if the vector had been manually expanded. #You can not create a vectored instance. PORT IN VECTOR<1:0> PORT OUT VECTOR_NAND_OUT INST NAND3 NAND VECTOR<1:0> VECTOR_NAND_OUT #INST NAND3 NAND VECTOR<1> VECTOR<0> VECTOR_NAND_OUT #The previous line is identical to this line. #End the definition of a logical block with the ENDDEF command. #ENDDEF must always occur before the next DEF. ENDDEF #Continue to define as many blocks as necessary. #The block at the top of the hierarchy MUST be named TOP. #Since every block that TOP uses must be defined above it, TOP must be defined at the bottom of the netlist. DEF TOP NET A NET Z INST A IO_IN A INST Z IO_OUT Z INST NAND1 NAND A true Z #true and false can be used to force inputs to specific values. ENDDEF

The primitives described below are the only ones which are predefined for use in the simulator. You are responsible for defining anything else you need using only these devices.

  • Logic
    • NAND
      Logical NAND gate
      A, B: The inputs to the NAND function.
      Z: The result of A NAND B.
      INST N1 NAND A B Z
  • Memory - None
  • IO (IO controls are displayed below the netlist window)
    • IO_IN
      Input port that allows the user to control one bit of data into the design.
      None (Input is done via user controlled IO control)
      Z: The value of the input port as controlled externally to the design.
      INST IN1 IO_IN Z
    • IO_IN8
      Input port that allows the user to control 8 bits of data into the design. The value may be specified as 8 binary bits (ex. 00110101) or 2 hex digits prefixed by 'x' (ex. x1F).
      None (Input is done via user controlled IO control)
      Z<7:0>: The value of the input port as controlled externally to the design.
      INST IN1 IO_IN8 Z<7:0>
    • IO_OUT
      Output port that allows the user to send one bit of data out of the design.
      A: The value to display externally.
      None (Output is done via IO control)
    • IO_OUT8
      Output port that allows the user to send 8 bits of data out of the design. The value is displayed in binary and hex simultaneously (ex. 11001010 (xCA)).
      A<7:0>: The 8 bit value to display externally.
      None (Output is done via IO control)
      INST OUT1 IO_OUT8 A<7:0>
    • IO_OUT7SEG
      Output port that allows the user to display data on a 7 segment display.
      A,B,C,D,E,F,G: The 7 controls of a 7 segment display.
      None (Output is done via IO control)

Our NAND gates are semiconductors and are primarily made of silicon (Si). You will need silicon when you sell designs. You'll need more silicon to make more complex designs. You can collect silicon by 'mining' on the Mine tab. You can also purchase upgrades which will increase your mining efficiency or automatically mine for you.

Silicon Mine:
Silicon (Si): 0
Mining skill (Si/attempt): 0
Auto miners: 0
Auto miner attempt rate (attempts/s): 0
Auto miner Si rate (Si/s): 0
Available Designs:

Design Description




Graphs enabled


Designs "blueprints" for research:

Completed designs for sale:

Version: ?
Automatically include prior designs




  • Mine Clicks: ?
  • Sell Clicks: ?
  • Total Mined: ?
  • Total Sold: $?
  • Completed Designs: ?


  • Prevent a reset from causing setInterval()s in init() to run twice
  • Do something to make it obvious how to debug by removing the test fixture and changing IO_OUTs to IO_INs
  • Add text to indicate that most tests are randomized
  • Prevent holding enter on sell buttons from working
  • Add confirmation to reset button
  • Show a popup if player tries to sell without enough Si or buy without enough $
  • Handle large number of clicks on sell buttons wrt analytics
  • Including IO_IN(8) should cause all tests to ultimately fail.
  • Display Si per NAND somewhere
  • Add more tests
  • Make max simulator speed upgrade do something
  • Add auto-selling feature
  • Add checkbox to select what design will be auto-sold
  • Collect and display more stats in info tab
  • Make more attractive
  • Balance everything
  • Make more fun


  • Tue May 6 13:18:53 UTC 2014Add ALUx8 design
  • Mon Apr 21 10:28:35 UTC 2014Add ADDx8 design
  • Fri Apr 11 15:36:51 UTC 2014Add BIN_TO_7SEG design
  • Fri Apr 11 15:36:51 UTC 2014Add IO_OUT7SEG output
  • Fri Apr 11 15:36:51 UTC 2014Add confirmation dialog when resetting
  • Thu Apr 10 17:09:26 UTC 2014Change Si to internally only have 2 decimal digits
  • Sat Apr 5 04:41:31 UTC 2014Add pop outs for tutorial 1 & 2
  • Fri Apr 4 20:06:25 UTC 2014Change dialog close to X
  • Fri Apr 4 18:32:38 UTC 2014Add error reporting code
  • Thu Apr 3 12:51:02 UTC 2014Display info about relative size of solution
  • Thu Apr 3 03:44:39 UTC 2014Adjust upgrade balancing
  • Thu Apr 3 03:44:39 UTC 2014Adjust design cost/price with new expectedNand values
  • Thu Apr 3 03:32:04 UTC 2014Make upgrades show current and next valueA
  • Fixed demux tests so that the name remains consistant between description and test
  • General release
  • Find beta testers
  • For IE we should at least detect the problem and alert the user to use a different browser
  • Host on google drive
  • Add google analytics
  • Display the $ per Si for each completed design on the sales area.
  • Add docs
  • Add tutorial
  • Make sure you can't pass a test that hasn't be purchased by changing the netlist to point to the unpurchased test.
  • Add upgrades like increase count of auto miners and auto sellers, decrease cost of NAND, increase Si per attempt,
  • Add Si and Money value/labels outside of tabs
  • Add money
  • Add design buying mechanic
  • Add selling mechanic
  • Get design testing mechanic working
  • Start integration of cyle simulator
  • Disable spell check on textareas
  • Get basic simulation working
  • Load netlist from file
  • Get primitives code into seperate file
  • Get designs code into seperate file
  • Need to keep track of design completeness and # nands used in each